1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor memory device. More particularly, the invention relates to a method of fabricating a flash memory device having control gate extensions.
A claim of priority is made to Korean Patent Application No. 2004-105911 filed Dec. 14, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memory devices can be broadly classified in two categories: volatile memory devices and non-volatile memory devices. Volatile memory devices are those that lose stored data when their power supply is interrupted, and non-volatile memory devices are those that retain data even when the power supply is interrupted. Because of their ability to retain stored data even when power is cut off, non-volatile memory devices are commonly employed in various portable, and/or removable devices including, for example, mobile communication devices, memory cards, etc.
One popular class of non-volatile memory devices are flash memory devices. A flash memory device comprises an array of flash memory cells, wherein each of the flash memory cells includes a cell transistor for storing data, and a driver circuit for driving the cell transistor. The cell transistor is formed in specific region of a semiconductor substrate designated as a “cell region” and the driver circuit is generally formed outside the cell region. In a typical flash memory device, the cell region generally contains at least several million cell transistors.
Flash memory devices can be classified into NOR flash memory devices and NAND flash memory devices based on the structure of their cell arrays. NOR flash memory devices have a cell array structure that allows random access to data stored therein. In contrast, the cell array structure in NAND flash memory devices only allows sequential data access to occur. For example, in a NAND flash memory device, data is generally accessed in units defined by “strings” in the device. A string is a structure in which a number of cell transistors is continuously arranged in an-active region having a line shape. Generally, the number of cell transistors in the string is a multiple of 2, e.g., 32. Data stored in the cell transistors is sequentially accessed by asserting a string select line to read out all data stored in the string. Because NAND flash memory devices use sequential data access, they are generally used for mass-storage devices such as various types of memory cards, but they are typically not used as computer memory.
FIG. 1 is a cross-sectional view of a conventional NAND flash memory device taken along the length of a word line in a cell region of the device. Referring to FIG. 1, an isolation layer 7 defining first and second active regions 1A and 1B is formed in a predetermined region of a semiconductor substrate 1. First and second active regions 1A and 1B are formed in parallel with each other and a control gate electrode 13 acting as a word line is formed across first and second active regions 1A and 1B.
Floating gates 10A and 10B are interposed between control gate electrode 13 and active regions 1A and 1B. In particular, a first floating gate 10A is interposed between control gate electrode 13 and first active region 1A, and a second floating gate 10B is interposed between control gate electrode 13 and second active region 1B. Floating gates 10A and 10B are insulated from control gate electrode 13 by an inter-gate dielectric layer 11, and furthermore, floating gates 10A and 10B are insulated from active regions 1A and 1B by a tunnel dielectric layer 3. Control gate electrode 13 also has a control gate extension 13A interposed between floating gates 10A and 10B.
Cell transistors CE1 and CE2 are formed at intersections between control gate electrode 13 and respective active regions 1A and 1B. In particular, a first cell transistor CE1 is formed at an intersection between control gate electrode 13 and first active region 1A, and a second cell transistor CE2 is formed at an intersection between control gate electrode 13 and second active region 1B.
A top surface of isolation layer 7 is generally positioned at a level above bottom surfaces of the floating gates 10A and 10B as shown in FIG. 1. Accordingly, parasitic coupling capacitors using isolation layer 7 as a dielectric layer may be formed between floating gates 10A and 10B. For example, a coupling capacitor C1 is formed by first and second floating gates 10A and 10B with isolation layer 7 interposed therebetween as shown in FIG. 1.
The capacitance of coupling capacitor C1 increases as a distance between floating gates 10A and 10B decreases. In addition, the capacitance of the coupling capacitor C1 increases as an effective cross-sectional area facing between floating gates 10A and 10B increases. As a result, as the degree of integration of NAND flash memory device increases, an inter-floating gate coupling capacitance between floating gates 10A and 10B increases.
Where the coupling capacitance reaches a certain level, it can cause malfunctions to occur in the flash memory device. For example, where first cell transistor CE1 is programmed, electrons are injected into first floating gate 10A to change its electric potential. The change in the electrical potential of first floating gate 10A causes an electric potential of second floating gate 10B adjacent to the first floating gate 10A to change due to coupling capacitor C1. As a result, a threshold voltage of second cell transistor CE2 changes and therefore a string including second cell transistor CE2 may malfunction in a read operation mode.
In order to prevent coupling capacitor C1 from interfering with the operation of first and second floating gates 10A and 10B, methods of extending control gate extension 13A to a level below bottom surfaces of the floating gates 10A and 10B have been investigated. For example, a NAND flash memory device addressing the inter-floating gate coupling capacitance problem and a method of fabricating the same are disclosed in U.S. Patent Application Publication No. 2004/0099900 (the '900 Application).
In the '900 Application, a plurality of control gate electrodes are formed across a plurality of parallel active regions, and floating gates are interposed between the control gate electrodes and the active regions. The floating gates are insulated from the active regions by a tunnel dielectric layer. Each of the control gate electrodes has extensions penetrating an isolation layer between the floating gates to levels below top surfaces of the active regions.
One problem with the approach taken by the '900 Application, however, is that a process of partially etching the isolation layer is required to form the extensions. The process of partially etching the isolation layer includes a wet etching process and a dry etching process. Unfortunately, it is very difficult to precisely control the depth of the etching produced by wet etching process. Where the wet etching process causes the isolation layer to be over etched, undercut regions can occur at lower regions of the floating gates and the tunnel dielectric layer can be damaged. In addition, the undercut regions can also cause a stringer defect when the control gate electrode is formed. Furthermore, the dry etching process uses the floating gates as etching masks, with the result that the floating gates and the tunneling dielectric layer may be damaged by plasma used in the dry etching process. Accordingly, exposed surfaces of the floating gates may be etched by the dry etching gas. Finally, the tunnel dielectric layer may be contaminated or damaged in the dry etching process due to a plasma transmission phenomenon.